DVL=VALID1, ALIGNMENT=RIGHT12, DMAWUFIFOSINGLE=DISABLED
Single FIFO Configuration
| ALIGNMENT | Alignment 0 (RIGHT12): ID[7:0], SIGN_EXT, DATA[11:0] 1 (RIGHT16): ID[7:0], SIGN_EXT, DATA[15:0] 2 (RIGHT20): ID[7:0], SIGN_EXT, DATA[19:0] 3 (LEFT12): DATA[11:0], 000000000000, ID[7:0] 4 (LEFT16): DATA[15:0], 00000000, ID[7:0] 5 (LEFT20): DATA[19:0], 0000, ID[7:0] |
| SHOWID | Show ID |
| DVL | Data Valid Level 0 (VALID1): When 1 entry in the single FIFO is valid, set the SINGLEFIFODVL interrupt and request DMA. 1 (VALID2): When 2 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 2 (VALID3): When 3 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 3 (VALID4): When 4 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. |
| DMAWUFIFOSINGLE | Single FIFO DMA wakeup. 0 (DISABLED): While in EM2 or EM3, the DMA controller will not be requested. 1 (ENABLED): While in EM2 or EM3, the DMA controller will be requested when the single FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] |